Timing closure has become increasingly difficult and presents some profound challenges in electronic circuit designs. The main goal of computer-aided design simulations is obtaining desired device electrical characteristics. Nonetheless, geometric dimensions and profiles of features of an electronic circuit design often have significant impact on the device electrical characteristics. The device dimensions which may have significant impact on the electrical characteristics include, for example, gate oxide thickness, gate width and length, shape of the poly gate at the bottom, and spacer width. As device geometry shrinks, semiconductor fabrication processes require more complex techniques to meet the design goals such as lower power supply, thinner gate oxides, shorter channel length, higher body doping concentration, and thinner silicon films. More importantly, the timing delay caused by the wires becomes more significant and can no longer be ignored.
As the device size continues to shrink and the clock frequency nevertheless increases, particularly into the deep-submicron regime, the electrical properties of wires or conductors become more prominent, and integrated circuit chips are more susceptible to breakdowns during fabrication due to, for example, the antenna effect or due to wear out or degradation over time due to, for example, electro-migration. Some prior methods propose prioritizing the nets and forcing shorter wire lengths among the high-priority, timing critical nets. However, making certain wires shorter usually comes at the expense of making other wires longer. Some other prior methods use larger gates with bigger transistors and higher drive strengths to charge the capacitance of wires more quickly and therefore making the path faster to maintain timing correctness without overly shortening some wires while lengthening others. However, there exists one problem for these methods. In electronic designs, the actual wire lengths are usually not known until some gates are physically in place occupying certain area(s) in the electronic circuit. Nonetheless, because larger gates also have larger capacitance and thus increases power and perhaps timing delay, the above method does not satisfactorily solve the problems caused by increasingly shrinking feature sizes. FIG. 1 illustrates a general method of timing closure, and FIG. 2 illustrates a method of timing closure with gate sizing.
Another problem with using larger gates is that larger gates with larger drive strength tend to worsen the problem of electro-migration. Deposited aluminum and copper interconnect have a polycrystalline structure from most fabrication processes; that is, these aluminum and copper interconnects are made of small grain lattices. Metal atoms can be transported between the grain boundaries. Electro-migration occurs during the momentum exchange between the mobile carriers and the atomic lattice as the current flow through the interconnect. As a result of the momentum exchange, metal tends to deposit in the direction of the electron flow, and voids thus form at the grain boundaries and reduce the conductivity. Such voids may over time cause the interconnect to stop conducting electricity altogether and thus cause the interconnect to fail.
Moreover, the continual effort to scale down electronic design features to the deep submicron region requires multilevel interconnection architecture to minimize the timing delay due to parasitic resistance and capacitance. As the devices shrinks to smaller sizes, the delay caused by the increased R-C time constant becomes more significant over the delay caused by the actual wire length. In order to reduce the R-C time constant, interconnect materials with lower resistivity and interlayer films with lower capacitance are required. However, the use of low-k dielectric material also aggravates the electro-migration problem due to the poor thermal conductivity of these low-k dielectric materials.
One way of resolving the aforementioned problems introduced by the continual reduction in feature sizes is to impose certain density rules for metal filling. Such rules typically comprise certain maximum and minimum densities within certain windows or areas on the chip. Some other rules impose different density limits among different window areas. Various tools and methods (see metal fill and slotting) have been developed or proposed for keeping the metal densities within the specified limits. However, the rules and equations used for estimating timing typically assume that the thickness of wires or conductors, at least for those on the same layer, is constant according to certain formulae, and therefore these rules and equations manipulate only the width of the wires to achieve the design goals.
Although this assumption of constant wire thickness arose out of a practical consideration and has worked while the thickness variation is relatively insignificant as compared to the geometry sizes, such an assumption appears to be outdated, especially in light of the current development in incorporating the topological variations of each film into the electronic designs and the continuously shrinkage in sizes of device features. Moreover, wire width cannot be arbitrarily altered due to the polycrystalline structure of the interconnect materials. As a result, additional methods have been developed to slot certain wires such that the metal densities within certain regions fall within the prescribed maximum and minimum limits.
Nonetheless, the above rule-based methods pose new problems and challenges in electronic designs. For instance, a good interconnect may be wrongfully determined to be improper for failing to meet the density rules or for producing unacceptable R-C delay even though the interconnect actually satisfies the design goals by having certain thickness that is different from the assumed value. A contrary example is that a bad interconnect unfit for the design intent or goals may nonetheless be wrongfully determined to be proper for meeting the metal density rules and/or the delay requirement. Furthermore, even among legal designs as bound by such limits, designers may nevertheless prefer different metal thicknesses in different parts of their designs. For example, a designer might prefer thin metal where minimum capacitance (C) is needed and thick metal where minimum resistivity or resistance (R) is required. A density limit, as typically specified now, does not tell how the thickness depends on density and does not express any relationship between density and thickness or the sign of such a relationship.
There are many existing approaches to timing closure. Typical timing closure approaches keep the gate delay constant under load by sizing the gates. The flaw in these approaches, as interconnects get longer, is that wire resistance can no longer be neglected as it usually is in these gate sizing approaches. Moreover, keeping the delay constant by sizing the gate offers reasonably accurate approximations only when there is no or insignificantly low resistance between the driving gate and the capacitive load. This is no longer true as the geometry continually shrinks, especially into the deep submicron technologies. Another approach by employing timing-driven placement methods may also be ineffective because these methods rely only on and are thus limited by the quality of the placement and the accuracy of the timing model. Furthermore, one common limitation of all these approaches is that these approaches only change the placement and/or the nominal, center-line routing.
With the advent of deep submicron technologies, resolution enhancement techniques (RET) have become one of the most important techniques to guarantee design for manufacturability (DFM). Nonetheless, applying these resolution enhancement techniques without taking the surface topology of certain features of the electronic design into consideration may pose further challenges to timing closure due to the continual pursuit for smaller geometry sizes and the use of shorter wavelengths on the lithographic tools such as the 193 nm λ ultra-high NA (numerical aperture) lithography or even the Extreme Ultra Violet lithography, especially in the deep submicron and increasing clock frequency designs. For example, in order to meet the increasing demand for higher resolution and finer geometries, the semiconductor industry has been pushing in order to obtain larger numerical aperture (NA) to achieve smaller minimum feature size. However, larger NA also decreases the depth of focus, and such decreased depth of focus causes the lithographic tools' ability to print accurate circuits to be more sensitive to the topographical variation of the films on the wafer.